1. Field of the Invention
The present invention relates generally to battery charger circuitry and in particular to circuitry which includes a power path switch and associated control circuitry.
2. Description of Related Art
Referring to the drawings, FIG. 1 is a simplified circuit diagram of a prior art battery charger 10. The charger is powered by a DC-DC switching voltage regulator which converts a DC input VBUS from an external power source to a DC output voltage VDD present on a system bus. In the present example, the regulator is a buck regulator which steps the input voltage down to a smaller output voltage. The regulator controller 12 includes a pair of switching transistors including a high side P type transistor 14 connected between the input VBUS and an inductor 18. A low side N type transistor is connected between the inductor 18 and circuit common. An output capacitor 20 in combination with inductor 18 function as regulator output filter. A fraction of the regulator output voltage VDD is sensed by a voltage divider made up of resistors 22A and 22B, with the divider output being fed back to one input of an error amplifier 24 of the controller. The second input to error amplifier 24 is either a reference voltage Vref, which is a fixed voltage of typically 1.2 V, and a variable voltage Vtrack to be described. The two voltages are selected by a multiplexer circuit 31.
As is well known, the controller 12 uses anti-phase drive to control the state of switching transistors 14 and 16, with the switching duty cycle being controlled to provide the regulated output voltage VDD where the sensed fraction of the output voltage is equal to reference voltage Vref which may be 1.2 voltage, by way of example. Assuming in this example that the charger is configured to charge single cell Li ion batteries, VDD is typically regulated to be about +4.4 volts once any battery connected to the charger has been fully charged. Charging accuracy is important for Li ion batteries since charging to a voltage of only 1% in excess of the specified voltage and charging to less than 1% of the specified voltage is undesirable.
The regulated output VDD is connected to a battery 30 to be charged by way of what can be referred to as a power path switch (PPS) 26. As will be described, switch 26 provides both a power path function and a regulator function, with control of these functions being carried out by a control circuit 34. In addition to providing a charging source for battery 30, output VDD operates to power the system, otherwise powered by the battery, when the battery is in a discharge state. As will be explained, the value of VDD varies from VDDMIN of +3 volts to a final value of +4.4 volts.
FIG. 2 is a timing diagram depicting a typical battery charging sequence. At time t1, battery 30 is in a deep discharge state having a voltage VBAT significantly less than 3.0 volts, that being the minimum system voltage VDDMIN. Initially, near time t1, transistor 26 is controlled to operate as a current regulator providing a relatively small fixed charging current. (Circuitry for sensing the charging current is not depicted.) Meanwhile, the system connected to the VDD bus is being powered by the switching voltage regulator at voltage VDDMIN. This is sometimes called the pre-charge mode. It should be noted that in the event external power source VBUS is not present when the battery is in the pre-charge mode, switch 26 it turned off to isolate battery 30. Battery 30 is also isolated when the charger is not in the pre-charge mode. By way of example, if VBUS is not present and there is no startup event such as detection of an activation of a power on switch or some kind of an alarm event, battery 30 is isolated to save power. Should the external power be applied at this time, switch 26 should be maintained off until VDD becomes greater than VBAT to avoid discharging the battery. Prior to time t1, when VDD is still smaller than VDDMIN, multiplexer 31 will select the fixed reference voltage Vref to be applied to error amplifier 24.
Eventually at about time t2, the small charging current will cause battery 30 to be charged up to the point that VBAT is around VDDMIN of +3.0 volts. At the point, multiplexer 31 will select Vtrack for regulating the value of VDD. In addition, transistor 26 is controlled by block 34 to operate as a linear voltage regulator where conductivity of the transistor is adjusted so as to maintain a constant voltage drop across the transistor and regulate a constant charge current into battery 30. Voltage Vtrack is derived from VBAT using a resistive divider made up of resistors 28A, 28B and 28C. A further voltage Vref′, also derived from VBAT, is used for the linear regulator control of transistor 26. The values of resistors 28A, 28B and 28C are selected to produce voltages Vtrack and Vref′ having a magnitude such that voltage across transistor 26 is maintained at 200 mV thereby fixing the voltage difference between VBAT and VDD at that value.
During this period, a relatively high constant current flows through transistor 26 to charge battery 30. Circuitry is typically provided to limit the maximum current charging level and to limit the battery temperature. At about time t3, the battery voltage has reached a final value of +4.2.
The time from t2 to t3 is typically referred to as the constant current portion of the charge cycle. During this period, as the battery voltage VBAT increases, the value of Vtrack also increases thereby increasing VDD so that the voltage across transistor remains at 200 mV. Note that transistor 26 is typically a large device having a RON value, when fully turned ON, of only 50 mΩ. However, when operating as a linear regulator, the ON resistance of transistor 26 is controlled to maintain the 200 mV. Once again, during this period the system connected to the VDD bus is powered by the switching voltage regulator.
At the end of the constant current portion of the charge cycle at T3, constant voltage portion of the charge cycle is entered. During this time, the voltage VBAT is regulated to specific voltage of +4.2 volts specified in this case by the battery manufacturer. In this constant voltage portion of the charging cycle the charging current will drop off fairly rapidly until the battery 30 is fully charged at some time soon after t4. At this point the charging current will drop to near zero. However, in order to provide head room for the operation of the linear regulator, the drain-source voltage of transistor 26 must be maintained above some minimum value, such as 200 mV in this example, to ensure that VBAT is held at the specified target voltage. Thus, even after the charging current has dropped to near zero, VDD must be greater than VBAT to provide a sufficient voltage difference for the operation of the linear regulator. The charging sequence is terminated when the charging current is reduced to 10% of the full value, with the power path switch 26 being turned OFF at this point so as to isolate battery 30.
When the external power source VBUS is present, the system power on VDD is provided by the DC-DC regulator as is the power for maintaining a charge on the battery. Transistor switch 26 effectively isolates battery 30 from the system load on bus VDD. When the external power is removed, transistor 26 is automatically turned fully ON so that the system is powered by battery 30 through the transistor.
The charger architecture of FIG. 1 provides a means for powering a system either from an external DC source or a battery. Further, the system can be powered even if the battery is deeply discharged. However, certain improvements can be made to improve efficiency and reliable operation, particularly with respect to the implementation and control of power path switch 26. As will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with drawings, one or more embodiments of the present invention provide significant improvements over the FIG. 1 approach.